Large die, UBM free WLCSP: A closer look

Development of low-cost WLCSP for large die with high I/O count is desired for broadening its applications. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5×5 mm2 with ball pitch smaller than 350 um.

At the ECT conference in Las Vegas TSMC discussed UFI (UBM-Free Integration) Fan-In WLCSP technology which they claim enables such large die fine pitch packages. 

TSMC has discovered that by controlling the maximum strain location and optimizing materials, chip warpage and the stress between Si and the PCB can be reduced which improves both component and board-level reliabilities of WLCSP packages. Packages of various die sizes, from 5.2×5.2, to 10.3×10.3 mm2 with both 400 and 350 um ball pitches have been developed.

In standard ball attach design, the under-bump metallurgy (UBM) is used as an interfacial layer between the metal pad of the integrated circuit and the solder ball. The growth of UBM/solder intermetallic compounds (IMC) limits the board level reliability of the package due to the poor mechanical robustness of the IMCs. When the die size is increased, the stress at the increases and facilitates crack formation at the UBM/solder ball interface. Extending the die size also results in higher chip warpage, which can negatively impact component-level reliability.
The fabrication cost of UFI WLCSP is lower than the cost of the conventional WLCSP due to the elimination of the UBM. Moreover, without the UBM structure, the thickness of the package can be 30% smaller than the conventional one.
The figure below compares the structures of a standard WLCSP vs the TSMC UFI WLCSP. In the UFI WLCSP, the solder balls are directly mounted to the Cu RDL followed by the PL (protection layer or passivation layer or polymer layer) deposition to secure the balls.

TSMC 1 Aug2016

Schematic structures of (a) conventional WLCSP, (b) UFI WLCSP
[Source: TSMC, 2016 IEEE ECTC Conference]

Simulation results showed the solder joint fatigue life decreases with increasing die sizes for both UFI and the conventional WLCSP. Predicted solder ball fatigue life was found to increases with decreasing die thickness. The authors suggest that decreasing the die thickness not only reduces the thermal expansion difference between the die and the PCB, but also causes the die to bend more under thermal loading. In addition, simulation results imply that solder joint creep strain for solder mask defined (SMD) structures is 72% higher than for non solder mask defined (NSMD) structures because of its reduced flexible solder joint height and the constraint of the solder mask. Thus they concluded that it is better to use NSMD type of PCB for UFI WLCSP.
The UFI WLCSP passes all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution, respectively. Large die UFI WLCSP has passed the component-level reliability tests of TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests.

TSMC 2 Aug2016

Summary of component level and board level reliability tests
[Source: TSMC,2016 IEEE ECTC]

The figure below shows the Weibull distributions of a conventional WLCSP with die size of 5.2 x 5.2 mm2 and 400 um ball pitch) , UFI with die size of 5.2 x 5.2 mm2 and 400 um ball pitch and UFI with die size of 7.2 x 7.2 mm2 and 400 um ball pitch) obtained by thermal cycling tests.

TSMC 3 Aug2016

Board-level thermal cycle Weibull distributions of conventional
WLCSP and UFI packages with different die sizes [Source: 2016 IEEE ECTC]

To demonstrate the possibility of higher interconnect density, they fabricated UFI- WLCSP with multiple RDL layers. The package with two RDL layers had die size of 10.3 x 10.3 mm2 and ball pitch of 350 um. The structure is shown below.

TSMC 4 Aug2016

Schematic diagram of 2-RDL structure [Source, TSMC, 2016 IEEE ECTC]

Reliability for the large die, two layer RDL package is shown below.

TSMC 5 Aug2016

Reliability test results for the large die, two layer RDL package [Source: TSMC, 2016 IEEE ECTC]

From Phil Garrou for Yole Développement