Substrates and panel processing at Semicon Taiwan 2015: a closer look

It is well known that > 50% of the cost of high density flip chip packaging is the substrate. It is therefore not surprising that materials and technology for high density substrate manufacturing has been the focus of much development work around the world. At the recent Semicon Taiwan 2015 Embedded and Wafer Level Package Technology Forum, several companies addressed the future of high density substrates through the use of glass as a substrate material and the use of panel based processing to increase throughput and thus reduce cost. Yole Développement thought this was worth… a closer look.

 Glass as a Substrate Material

DC Hu of Unimicron reviewed glass as a candidate material for high density substrates and interposers.
While large glass panels are available at a reasonable cost, it is not yet clear that the technology and /or equipment are currently available to put glass packaging into mass production. Never-the-less, it is certainly worth the effort to develop the data and sort this issue out.
One of the main questions regarding glass has been how to make small, electrically and mechanically functional, vias and fill them with conductive metals. Hu points out that the following parameters need to be evaluated:
• TGV Diameter:
– Top – Bottom – Taper ratio
• TGV Roundness
• TGV Quality
– Cratering – Chipping – Cracking
• Surface Roughness
• Via Position Accuracy
• Via Forming Speed
Hu compares the current via forming capability of Via Mechanic, LPKF and Corning as is shown below.

It appears that the most advanced systems are currently developing < 100um glass thickness, ~ 25um holes at a throughput of > 2000 holes/sec.
Glass is also being examined as a laminated core replacement material as shown below. Glass has a 3X better flatness (R < 0.5mm) than an organic core given the same core CTE (i.e. 3 ppm/?C). Such technology is currently being demonstrated at 508 x 508mm; 100-200um glass thickness; with 8/8um L/S on ABF dielectric.

To evolve this technology to high density (i.e. 2/2 L/S ) Hu predicts they will require:
• Large panel level exposure system
• High resolution and sensitivity photoresist materials
• Thickness uniformity of photoresist on panel
• Control of seed layer removal
• Optimized dielectric materials
• Control of warpage during asymmetric build
They have demonstrated such capability on test vehicles as shown below

Fraunhoffer IZM – Panel Level Processing
Tanja Braun and co-workers at IZM/TUB detailed their studies on fan out panel level processing. They listed the following as the most obvious challenges:
Warpage (for both Assembly & Manufacturability)
• Heterogeneous materials and non-symmetric structure cause bow
• Polymer materials with adapted CTE& modulus and low shrinkage are required
• Optimized layer sequence and design required
Accuracy/Resolution
• Improved optical recognition systems for placement equipment
• Die shift compensation
• Imaging with high depth of focus and high resolution
• Local alignment – LDI or scanner or stepper
Yield (and thus Cost)
• Suited materials and components
• Optimized processes
• Production experience
Low k Polymers for RDL
• Standard epoxy polymers are not sufficient for high performance RDL
• Low k with low loss are essential for RF performance
• Dry-film polymers offer the possibility for thick polymer layer beneficial for RF
They showed the equipment they have put in place for ~ 600 x 450 panel level processing:

They are currently limited to ~ 10um L/S. 

Examining pick and place and the molding operations they have:
– Placed 5,600 chips (2 x 3 x 0.25mm) on the panel with an assembly speed of ~ 6.500 chips/hr – compared both liquid and granular mold compounds in their compression molding operation on panels with assembled dies. Granular EMC shows better mold times and shown granular EMC shows better mold results and shorter process time
– found that die shift is best controlled by placing both global and local (by quadrant) “fiducial dies” first and then placing other dies with respect to fiducial dies.
They currently conclude that high density panel level processing will require “new materials in combination with new processes”

J Devices – Panel Level Processing (PLP)
J Devices is equipping a PCB facility they purchased from Sony to manufacture this PLP technology.
J Devices indicates that the required RDL technology depends on the application. For example Application processors will require wafer grade photolithography while modules for RF/PMIC will only require PCB grade photolithography.
Similar panel level processing is being developed by ASE/TDK (SESUB – Semiconductor Embedded SUBstrate) and AT&S – (ECP – embedded component packaging).
Their standard PLP process flow is shown below:

An example of an Rf/PMIC (power management IC) module fabricated in PLP is shown below.

Source : Dr. Phil Garou