The growth of the thinned wafer: 32 million 8-inch WSPY by 2020…
It is well-known that semiconductor devices are getting smaller and smaller year after year for the same functions due to the implementation of Moore’s law for IC devices and also due to the pressure on production costs driving die surface shrinkage. But the same trend is happening on the z axis: many devices need to be thinner and thinner. Why? Several reasons are driving this decrease in the thickness of devices.
Consumer applications such as smartphones, smart cards and stacked packages are clearly driving this trend but also technical reasons are also pushing in that direction, for example to increase the heat extraction from modules, increase the power efficiency of power devices, etc. One of the incredible uses of thin wafers is image sensors. Sony and several other companies have been able to process the readout circuit (the numerical part of the image sensor) and the optical part (the photo diode, the color filters, etc.) on totally different manufacturing lines (leading edge CMOS line for the IC circuit, dedicated CMOS image sensor line for the optical part), thin them and bond them at wafer level in order to have a very thin image sensor made of 2 stacked wafers…
This area is heavily impacting the semiconductor industry: we are talking about almost 32 million 8-inch WSPY by 2020… To know more, take a look at the Yole Développement (Yole) report dedicated to these thinned wafer technology trends and related equipment markets…
(Thin Wafer Processing and Dicing Equipment Market report – Yole Développement)
We estimate that the number of thinned wafers used for MEMS devices, CMOS Image Sensors, memory and logic devices, including those with TSVs, as well as Power devices, exceeded the equivalent of 16.5 million 8-inch wafer starts per year (WSPY) in 2015 (see the new report published by Yole on “Thin Wafer Processing and Dicing Equipment Market” for more details). This is mainly supported by CMOS Image Sensors, followed by Power devices. We expect that this number of thinned wafers will peak at the equivalent of almost 32 million 8-inch WSPY by 2020. This would represent a 14% compound annual growth rate (CAGR) from 2015 to 2020.
Thinner wafers bring several benefits, including enabling very thin packaging, and therefore better form factors, improved electrical performance and high heat dissipation. Miniaturization towards smaller, higher-performing, lower-cost device configurations has thinned wafers below 100 µm or even 50 µm for some applications, such as memory and power devices. Such very thin wafers are putting challenges on the manufacturing side. Today, grinding is the most conventional thinning process used by semiconductor applications, reducing wafers from an average starting thickness of 750 μm to 120 µm. However, below 100 µm, silicon wafers become very flexible and challenging to thin down further using only standard grinding methods due to stress in high volume manufacturing production. Segments such as memory and logic require additional thinning steps such as chemical-mechanical planarization (CMP) in order to remove micro cracking and edge chipping caused by the standard grinding process. Backside illuminated CMOS Image Sensors are among the only applications using wet/dry processes and CMP since they need the maximum number of back grinding process steps to obtain the best die quality possible.
(Thin Wafer Processing and Dicing Equipment Market report – Yole Développement)
But the main changes are happening on the dicing side: dicing wafers as thin as 50µm is becoming very, very challenging…
Reaching more than $100M in 2015, the dicing equipment market will double by 2020-2021. Yet at the same time thin wafers are creating new challenges of significant interest in the dicing equipment industry such as die breakage, chipping, low die strength, handling issues and dicing damage.
Today, the most common dicing technology applied across memory, logic, MEMS, RFID and power devices is mechanical dicing, also known as blade dicing. However, we are seeing a trend towards adopting alternative dicing technologies. These include stealth dicing and plasma dicing based on deep reactive ion etching technology. Memory in particular has predominantly relied on a combination of blade and laser dicing applied together to singulate complex stacks. Using only blade dicing on top layers leads to delamination issues because of the high metal density. However, it is difficult to safely singulate 50 µm thin wafers even with laser dicing and this could allow plasma dicing to enter this area. In MEMS devices, blade dicing is largely applied for singulating the ASIC, capping and MEMS sensors. However, exposure to water from the process can contaminate some sensors and destroy sensitive MEMS structures, e.g. in MEMS microphones. In such cases, stealth dicing has already been adopted in large volume production.
Plasma dicing has also been adopted in volume production today for MEMS devices and RFID to reduce die fragility, boost die strength, increase the number of chips per wafer and thus reduce Cost Of Ownership of equipment overall. This promising method will grow in the semiconductor area and could reshape the dicing landscape, enabling new equipment suppliers to enter that market.
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