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NEO semiconductor releases technology CAD (TCAD) simulation data for ground-breaking 3D X-DRAM

NEO Semiconductor, a developer of innovative technologies for 3D NAND flash and DRAM memory, announced findings of 3D X-DRAM™ simulations . Semiconductor manufacturers and engineers use TCAD to simulate emerging technologies and optimize new products.

Explorations of TCAD models and simulations reveal that 3D X-DRAM supports:

  • < 1 V (volt) operation voltage.
  • < 3 ns (nanosecond) write time (cell level).
  • > 20 uA (microampere) sensing margin.
  • > 100 ms (millisecond) data retention time.
  • > 10ˆ16 (10 quadrillion) endurance cycles.

“Semiconductor manufacturers rely on TCAD tools to accelerate development and optimize products using virtual experiments rather than physical ones,” said Andy Hsu, Founder and CEO of NEO Semiconductor and an accomplished technology inventor with more than 120 U.S. patents. “We use these same tools to create models and run simulations demonstrating the feasibility of adopting 3D X-DRAM technology to bring 3D DRAM products to market.”

3D X-DRAM uses innovative Floating Body Cell (FBC) technology with one transistor and zero capacitors for each data bit. A simple 3D structure makes 3D X-DRAM less risky and costly than 3D DRAM alternatives. Manufacturing 3D X-DRAM involves a self-aligned, 3D NAND-like process with high yields. NEO estimates 3D X-DRAM achieves 128 Gb density with 230 layers—4 times better than 2D DRAM.

“A new memory architecture with 3D DRAM technology will represent the future of memory in order to accelerate and scale DRAM to new levels,” said Jay Kramer President of Network Storage Advisors. “NEO Semiconductor is the way with an innovative design that not only will address new levels of performance, reduced power consumption and smaller footprint but will be the first to power the next generation of memory that can enable new applications in the marketplace.”

NEO Semiconductor will give an invited speech about 3D X-DRAM in the 16th IEEE International Memory Workshop (IMW) being held May 12th-15th, 2024 in Seoul, Republic of Korea. Andy Hsu, CEO will release additional TCAD Simulation Results for this ground-breaking technology. Interested parties are invited to request a meeting with NEO’s management by contacting mayalustig@neosemic.com. IMW is sponsored by the IEEE Electron Devices Society and designed to gather the memory community to discuss technologies, applications, strategies, and markets.

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