High-End Performance Packaging 2024

Table of contents 

• Glossary
• Identity card 
• Semiconductor PACKAGING ACTIVITY  
• Report Objectives
• Key features of this report
• Companies cited  
• What we got right, what we got wrong                                     
• Methodology and definition 
• 3-Page summary 
• Executive summary 
• Introduction  
  • Semiconductor Industry
  • The pursuit of Moore’s Law
  • High-end performance packaging definition
  • Package family segmentation
  • High-end performance packaging: all platforms
• Market forecasts  
  • Package ASP split by technology 
  • Market Size - Revenues
  • Market Size – Units & Wafers  
  • Market size split by technology 
    • 3D SoC  
    • 3D Stacked memory
    • UHD FO / RDL Interposer
    • 2.5D Interposers
    • Embedded Si bridge
  • Chapter conclusion

Market trends  

• Application
• Data center
• AI and Graphics
• CPU
• Autonomous vehicles 
• Chapter conclusion  

Technologies Trends

• Roadmap
  • Technology Overview
  • By 2.5D and 3D Technology Trends
  • By Interconnect density and technology node and packaging revenue
  • By application technology
  • By I/O density, I/O pitch and package size
  • Si Interposer, Si bridge, 3D stacking and HB key parameters 
• Interposer Trends
  • Interposer Trend Overview
  • By TSMC, Samsung, and Intel
  • RDL Interposer
  • Different Interposer material comparison
• Si Bridge Trends
  • By Intel, TSMC and SPIL, and other players
  • Chip-first or chip-last option
  • Si bridge vs. RDL interposer vs. Si Interposer
• 3D Trends
• Chiplet and heterogeneous integration 
  • Definition
  • Why chiplets?
  • Cost and economics of chiplets
  • Commercialized products
  • Chiplet Ecosystem
  • Chiplet activities
  • Chiplet based heterogeneous integration
  • Homogeneous vs heterogeneous integration
  • Conclusion
• Hybrid bonding 
  • Why use hybrid bonding for 3D integration?
  • HB Technology 
  • Supply chain
• Co-Packaged Optics
  • Introduction
  • CPO industry and supply chain
  • CPO challenges
  • Conclusion
• Glass core substrates
• Chapter Conclusion

Commercialized Products

• Product launched timeline –overall
• 3D Memory
• FPGAs
• xPU
  • Intel Emerald Rapids and future
  • Intel Ponte Vecchio
  • Intel Meteor Lake
  • Intel: Moving beyond Meteor Lake
  • Intel Gaudi
  • Apple M2 Ultra
  • TSMC 3D-SOIC in AMD’s V-cache
  • AMD Ryzen & Epyc
  • AMD Radeon
  • AMD Instinct MI300
  • Nvidia H100
  • Nvidia H200 & Blackwell
  • Google Tensor
  • Broadcom
  • Microsoft Maia 100
  • Amazon
  • Jasminer X4-Q
  • Chapter conclusion
• Supply Chain
  • Overview
  • Global mapping based on HQ
  • Business Model: Who is doing what?
  • Mapping of players based on technology
  • Key player: Intel, Samsung and TSMC
  • Adoption and deployment of 2.5D/3.0D in China
  • China chiplet league
  • Noteworthy news on technologies
  • Chapter conclusion

Report Conclusion

Yole Group Products

About Yole Group

High-end Packaging market will exceed $28B by 2029, with a whopping 37% CAGR2023-2029

The High-end Packaging market was worth $4.3B in 2023 and is projected to reach over $28B by 2029, with a CAGR2023-2029 of 37%. Breaking it down into its end markets, the biggest High-end Performance Packaging market is ‘Telecom & Infrastructure,’ which generated over 67% of the revenue in 2023. It is followed closely by ‘Mobile & Consumer,’ the fastest-growing market with a 50% CAGR. In terms of package units, High-end Packaging is projected to experience a 44% CAGR2023-2029 from 627M units in 2023 to 5.6B by 2029. This huge growth is explained by the fact that in the case of high-end packages, the demand is increasing healthily, and the ASPs are very high compared to less advanced packaging as there is a transition of value from the front-end to the back-end forced by 2.5D & 3D platforms.

3D Stack memory – HBM, 3DS, 3D NAND & CBA DRAM – are the most significant contributors and will represent more than 70% of the market by 2029. The fastest-growing platforms are CBA DRAM, 3D SoC, Active Si Interposer, 3D NAND stack, and embedded Si bridge.

High-end Performance Packaging is creating waves of disruption in the semiconductor supply chain.

Foundries, IDMs, and OSATs compete in the same High-end Packaging market space, blurring FE to BE supply chain boundaries. This has made it harder for smaller players to compete meaningfully. The barrier to entry in the High-end Packaging supply chain is increasingly high, with major players disrupting the advanced packaging domain with their FE capabilities. The adoption of hybrid bonding makes things more difficult for OSATs, as only players with fab capabilities and ample resources can afford significant yield losses and large investments.

TSMC is present with its 3D Fabric leveraging CoWoS, InFO, and 3D SoIC solutions. Intel uses its Foveros, EMIB, and Co-EMIB products and later Foveros Direct & Omni. Samsung is the pioneer in HBM and 3DS memory, and is providing I-Cubes, H-Cube, and later R-Cube & X-Cube as well. TSMC dominates the FE+BE high-value manufacturing business from a technological point of view. It has proved superior in every key business aspect, from development, production, and investment to IP filing. At this rate, TSMC is not simply trying to kill off its business competitors (Intel and Samsung) but makes sure to remain the industry leader. The Taiwanese giant provides its InFO_SoW solution to Tesla and Cerebras, and its 3DSoIC, CoWoS, and InFO solutions are used by players such as AMD, Xilinx, and GUC for their new products.

Intel is the key player for on-shoring chip manufacturing and advanced component packaging for the U.S. Its ‘Lakefield’ Foveros packages are sold to end customers such as Samsung, Microsoft, and Lenovo. More products based on Intel’s advanced 3D/2.5D packaging technologies, such as Ponte Vecchio, Meteor Lake, Foveros Omni, and Foveros Direct, will hit the market soon.

Samsung Electronics is a pioneer in developing 3D TSV stacking technology for HBM memory and one of the few players that has invested in this technology since the 2000s. Also, Samsung Electronics has been running Samsung’s DDR4 3D 256GB Dual Inline Memory Modules (RDIMMs) production since 2015. Additionally, the Korean giant recently developed its I-Cubes and H-Cube solutions.

Since 2015, Sony has been the company that has shipped the most units of hybrid bonded chips using W2W technology. Sony currently ships 2-stack and 3-stack versions. In the 2-stack, the pixels are on top of the circuitry. In the 3-stack version, pixels are stacked on top of a DRAM buffer cache, which is on top of the circuitry. In 2020, Sony introduced a D2W solution for its SWIR imager.

The realization of High-end Packaging is now increasingly dependent on FE technology, and hybrid bonding is becoming a new trend. BESI is playing a critical role in this new trend, supplying equipment to big players such as TSMC, Intel, and Samsung, all of which are competing for supremacy.  Securing next-generation high-end performance business is financially and technically beyond the capabilities of OSATs and substrate suppliers.

Semiconductor packaging technology is the key pillar if the future is digital – yet Moore’s Law is reaching its limit.

Fueled by digital end-system demands and technological innovation, High-end Packaging options are increasingly rich and groundbreaking. Existing production of 2.5D and 3D integration capabilities are the benefits gained from investment in the past, growing from the laudable desire to meet requirements with long-term ambitions. Performance/power improvements at the escalating cost associated with Moore’s Law scaling triggered the semiconductor industry to strategize system-level scaling with High-end Packaging solutions instead of purely scaling FE advanced nodes. SoC partition and ‘chiplet’ integration is a potential path forward to optimize the scaling cost by partitioning SoC chips and scaling only those most critical circuit blocks. To achieve this, 2.5D and 3D heterogeneous integration technology with high interconnection density, high bandwidth, and high power efficiency are required.

In the High-end Packaging technology segmentation, we have classified key technologies by IO pitch and IO density: UHD FO, 2.5D interposers, 3D stacked memory, and embedded Si bridge as 3DSoC (hybrid bonding). Leading players are starting to gain market share with core technologies in UHD FO, interposers, TSVs, and embedded Si bridges. Moreover, these technologies can be further combined and co-exist to fulfill future needs, for example, in Intel’s Co-EMIB (EMIB + Foveros) and TSMC’s InFO_LSI (UHD FO + LSI).

A future-generation packaging solution is to achieve a denser 3D IC at a system level of ≤10 μm fine pitch. Leading suppliers, especially TSMC, YMTC, Samsung, and Intel, are all targeting this by providing cutting-edge hybrid bonding solutions, representing the contact point between the semiconductor and packaging worlds. The possibilities of mix-and-match high-end and customized components can be unlocked under one key technology: hybrid bonding.

The primary technology trend for all high-end performance packaging platforms is reducing interconnection pitch no matter the type – it is related to TSVs, TMVs, microbumps, and even hybrid bonding, which is already the most aggressive solution. On top of that, via diameter and wafer thickness are expected to be lowered. This technology evolution is necessary for integrating more complex monolithic dies on the one hand and chiplets on the other to support faster data processing and transmission while ensuring less power consumption and loss and allowing higher density integration and bandwidth for future generations. The general trend is to have more 2.5D platforms combined with 3D platforms in the same package. Therefore, we expect packages integrating chiplets using 3D SoC, 2.5 interposers, embedded silicon bridges, and MTV co-packaged optics in the same package in the future. New 2.5D & 3D packaging platforms will hit the market later, making HEP packaging much more complex.

Accretech, Adeia, ADI, Alibaba group, Amazon, AMD, Amkor, Applied Materials, ARM, ASE, ASMPT, Atmel, Atos, Baidu, Besi, Biren Technology, Blue Ocean Smart System, Brewer Science, Broadcom, BroadPak, Cambricon, Canon, Casmeit, CEA-Leti, Cerebras, Corning, Cray, Cyber Optics, Cypress, Disco, Dupont, Ebara, Eliyan, Empyrean, Entegris, EVG, Facebook, Foxconn, Fraunhofer IZM, Freescale, Fujitsu, Global Foundries, Gloway,  Graphcore, GUC Glink, Hanni, HD Microsystems, Hi-Silicon, HLMC, Hua Tian, Huawei, Ibiden, IBM, IME, IMEC, Integra, Intel, Infineon, Invensas, ITRI, JCET, Juniper Networks, Kioxia, KLA, Kyocera, Lam Research, Lapis Technology, LB Semicon, Marvell, Mediatek, Meta, Micron, Microsoft, Micross Components, Mitsubishi,  NEC, Nepes, Nhanced Semiconductors, Nokia, Nvidia, Ommi Vision, onsemi, ONTOS TT, Oracle, Panasonic, Plasma Therm, PRC Georgia Tech, Protean Tecs, PTI, PVA Tepla, Qorvo, Qualcomm, Quavo, Raytheon Technologies, Renesas, RISC-V, Rohm, Samsung, Sandia National Laboratories, Sanyo, Semco, Semsysco, Set, Sharp, Shinetsu, Shinko, Showa Denko, Siemens, Silicon Box, SK Hynix, Skywater, SMIC, Sony, SPIL, SPTS, ST Microelectronic, Sunlune, Surfx Technologies, TI, Suss Microtec, Synopsys, TEL, Tencent, Tesla, Tezzaron Semiconductor, TFME, Tokyo Electron, Toshiba, Tower Semiconductor, Nanya, TSMC, UMC, Unimicron, Unity SC, Ventana, Western Digital, Xilinx, Yibu Semi, YMTC, and more.​

Key Features ​

The High-end Packaging market was worth $4.3B in 2023 and is projected to reach over $28B by 2029, with a CAGR2023-2029 of 37%. Breaking it down further into its end markets, the biggest High-end Performance Packaging market is ‘Telecom & Infrastructure,’ with over 67% of the revenue in 2023. It should be followed closely by the ‘Mobile & Consumer’ which is the fastest growing market with 50% CAGR. In terms of package units, High-end Packaging is projected to experience a 44% CAGR2023-2029, from 627M Units in 2023 to 5.6B by 2029. The top fastest-growing platforms are CBA DRAM, 3D SoC, Active Si Interposer, 3D NAND stack & embedded Si bridge. ​

What’s new? ​

• New technology platforms added: CBA DRAM​
• New technology trend information added: CPO, Glass substrate; ​
• New product and supply chain update;​
• New assumptions;

Report's objectives: ​

• Identify and describe which technologies can be classified as ‘High-end Performance Packaging’​
• Define High-end Performance Packaging​
• Analyze key market drivers, benefits, and challenges of High-end Performance Packaging, by application ​
• Describe the different existing technologies, their trends, and roadmaps​
• Consider the supply chain and High-end Performance Packaging landscape​
• Update the business status of High-end Performance Packaging technology markets​
• Provide a market forecast for the coming years, and estimate future trends​
• ​

High-end Performance markets are studied from the following angles:​

• Top-down, based on end-system demand​
• Market valuations based on top-down and bottom-up models​
• Market shares, based on production projections​
• Supply value-chain analysis​
• State-of-the-art technologies and trends​
•  End-user application adoptions