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Applied Materials unveils eBeam metrology system that enables a new playbook for patterning advanced logic and memory chips

  • Edge chip designs require a new class of metrology that goes beyond optical target-based approximation, statistical sampling and single-layer control
  • PROVision® 3E system combines nanometer resolution, high speed and through-layer imaging to give engineers the millions of datapoints they need to correctly pattern the most advanced chip designs
  • 30 systems already installed at the world’s foundry-logic, DRAM and NAND customers

Applied Materials, unveiled a unique eBeam metrology system that enables a new playbook for patterning control based on massive on-device, across-wafer and through-layer measurements.

Advanced chips are built one layer at a time, and each of billions of individual features must be perfectly patterned and aligned to create working transistors and interconnects with optimal electrical characteristics. As the industry increasingly moves from simple 2D designs to more aggressive multipatterning and 3D designs, a commensurate breakthrough in metrology is needed to perfect each critical layer and enable the best performance, power, area-cost and time to market (PPACt™).

Traditional Patterning Control Playbook

Traditionally, patterning control has been achieved using optical overlay tools that help align die patterns with “proxy targets” which are guide marks printed into the spaces between die that are removed from the wafer during die singulation. Proxy target approximation has been complemented with statistical sampling of a small number of die patterns from across the wafer.

However, after successive generations of feature shrinking, broader adoption of multipatterning, and the introduction of 3D designs that cause interlayer distortions, the traditional approach is to measurement deficiencies – or “blind spots” – that are making it more difficult for engineers to correlate intended patterns with on-die results.

New Patterning Control Playbook

The PROVision 3E system includes technical features that enable patterning control of most advanced designs, including 3nm foundry-logic chips, gate-all-around transistors and next-generation DRAM and 3D NAND.

Resolution: Applied’s industry eBeam column technology provides the highest electron density available, enabling detailed imaging at 1nm resolution.

Accuracy: Decades of CD SEM system and algorithm expertise deliver accurate and precise measurements of critical features.

Speed: 10 million accurate, actionable measurements per hour.

Multi-Layer: Applied’s unique Elluminator ® technology captures 95 percent of back-scattered electrons to quickly measure critical dimensions and edge placement at multiple levels simultaneously.

Range: A broad range of eBeam energies. High-energy modes enable rapid measurement, hundreds of nanometers deep. Low-energy modes enable damage-free measurement of fragile materials and structures including EUV photoresist.

Together, these features enable customers to move from the old patterning control playbook – composed of optical proxy target approximation, limited

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