Panel Fan-Out ramps, challenges remain

An article written by Mark Lapedus for Semiconductor Engineering – Cost and the lack of a panel-size standard gives fan-out a slower start. After years of R&D, panel-level fan-out packaging is finally beginning to ramp up in the market, at least in limited volumes for a few vendors.

However, panel-level fan-out, which is an advanced form of today’s fan-out packaging, still faces several technical and cost challenges to bring this technology into the mainstream or high-volume manufacturing. Moreover, several companies are developing the technology using different panel sizes, but there is a need for a standard format. The lack of a panel-size standard makes it difficult for equipment makers to commit resources and develop systems for panel fan-out.

In production for several years, today’s fan-out technologies involve packaging a die in a round wafer format in 200mm or 300mm wafer sizes. TSMC’s InFO technology, the most notable example of fan-out, is being used in Apple’s latest iPhones.

In panel-level fan-out, though, the package is processed on a large square panel. In one theoretical example, a 500mm x 500mm panel can process 4.54 times as many die as a 300mm wafer, according to a recent paper from STATS ChipPAC and Rudolph Technologies. By increasing the number of die per substrate, a vendor could see huge productivity gains and lower costs over today’s fan-out processes… Full article

Fig.1 – Comparison of number of die exposed on 300mm wafer to number of die on panel. Source: STATS ChipPAC, Rudolph

Fig. 2 – Who is doing what in panel fan-out. Source: Yole Développement