Samsung gears up for 3D chip packaging revolution with SAINT technology

By Kamlesh Bhati for Sparrowsnews.

In a strategic move set to reshape the semiconductor landscape, Samsung Electronics is poised to launch its ‘3D packaging’ business next year. This innovative approach involves vertically stacking heterogeneous semiconductors, heralding a new era of high-performance and low-power artificial intelligence (AI) chips. As the demand for more advanced and efficient AI semiconductors intensifies, the market is projected to soar to a staggering $78 billion by 2028.

Unlike traditional horizontal chip placement, 3D Chip packaging involves stacking chips vertically. This configuration facilitates faster data processing between semiconductors and significantly enhances power efficiency. With customers increasingly seeking high-performance, low-power AI semiconductors, Samsung’s venture into 3D chip packaging comes at a pivotal moment.

Driving this initiative is the utilization of the cutting-edge semiconductor packaging innovation known as ‘SAINT’ (Samsung Advanced Interconnection Technology). This innovative process involves connecting different types of chips to operate cohesively as a single unit. In contrast to conventional horizontal placement, 3D packaging distinguishes itself by vertically stacking chips.

Samsung Electronics has successfully concluded the technical verification of ‘SAINT-S.’ This specific iteration involves the stacking of SRAM, serving as temporary data storage, on top of a processor, such as a central processing unit (CPU). Looking ahead, Samsung aims to finalize the technology verification of ‘SAINT-D’ in the upcoming year. ‘SAINT-D’ entails the placement of DRAM for data storage on top of processors, including CPU and graphics processing unit (GPU). Furthermore, ‘SAINT-L’ is in the pipeline, designed to position processors like the application processor (AP) both above and below the stack. These strategic advancements underline Samsung’s commitment to pioneering advancements in semiconductor technology

The move towards 3D packaging is fueled by the limitations of ultra-fine processing technology, which constrains the downsizing of individual chips. Semiconductor companies, including Samsung, are focusing on packaging as a critical process to improve performance by skillfully arranging and connecting manufactured chips. The importance of this packaging process is expected to escalate, with the high-tech packaging market forecasted to grow from $44.3 billion in the previous year to an impressive $78.6 billion by 2028, according to Yole Intelligence.

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Source: sparrowsnews.com