Primarily designed to simplify the control of power devices in the automotive, industrial, and consumer areas, BCD technology combines three types of transistors on the same die: Bipolar for analog functions, CMOS (Complementary Metal-Oxide-Semiconductor) for digital functions, and DMOS (Double-diffused MOS) for power functions and high voltage regulation.
This 3-in-1 integration offers the considerable advantage of a reduction in PCB footprint, chip area, and electromagnetic interferences. With new BCD technologies, manufacturers aim to add improved power features to high-density digital and analog functions. This requires a thicker gate oxide layer and more complex isolation techniques.
Almost 40 years after being imagined and developed by the Franco-Italian semiconductor manufacturer STMicroelectronics, how much progress has been made on this technology, with which processes, and at what cost?
Sylvain Hallereau and Belinda Dube, both Technology & Costs Analysts at Yole SystemPlus, part of Yole Group, have examined this question via in-depth technological and cost analyses based on the study of 49 BCD components manufactured by the major industry players in the BCD Technology and Cost Comparison 2023 report.
The keys to the success of a smaller technology node: advanced isolation methods, metal layers, and MIM capacitors
As higher voltage breakthrough and transistor density are targeted, the traditional LOCal Oxidization of Silicon (LOCOS) isolation technique has been largely superseded since 2008 by more advanced techniques. Shallow trench isolation (STI) is used in CMOS transistors to create active structures with smaller and closer isolation, contributing to higher component packing and overall better circuit performance and reliability. For high voltage functions, the etch deepness used in STI is insufficient to enclose the charged particles efficiently. In this case, deep trench isolation (DTI) is preferred.
However, this approach involves two additional masks and cannot be used to create the gate oxide of a lateral DMOS transistor. In this type of component, the outcomes delivered by STI are not as favorable as those using the LOCOS method, which remains relevant in scenarios where high voltage is not essential. To achieve more functionalities and a smaller technology node, BCD technology now very commonly includes a combination of two techniques (STI/DTI, LOCOS/DTI), or even three in some cases (LOCOS, STI and DTI), which renders the manufacturing process even more complex.
In addition, the silicon-on-insulator (SOI) substrate ensures perfect isolation between the different transistors and is a ‘must-have’ solution for high-voltage devices. Other techniques (galvanic isolation, SiO2-based capacitive isolation barrier, and Multi Floating Field Plate (MFFP)), recently introduced and increasingly adopted, are also described in the Yole SystemPlus report BCD Technology and Cost Comparison 2023.
With a greater digital function complexity shrunk into a smaller die, more metal layers are integrated to ensure the CMOS transistor interconnections. Frequently found in aluminum (case of NXP 0.14 µm BCD technology with six layers), the emergence of copper layer integration is observed (case of Infineon SPT9 0.13 µm BCD technology with five copper layers, or Intel PMB6829 0.065 µm BCD technology with six copper layers and one aluminum layer). Thanks to its intrinsic properties, the copper reduces the gate delay for the digital function, improves electromigration ruggedness, and enhances thermal management.
New BCD technologies also feature MIM (metal-insulator-metal) capacitors that can be stacked onto any of the metal layers that act as the first electrode. This architecture allows more functions to be added without any consequence on the die area.
Impact on the cost and supply chain
Advanced isolation techniques and the integration of additional metal layers and MIM capacitors imply a more complex manufacturing process and require specific equipment. From less than 20 masks for the old generations, the manufacturing process now involves an average of more than 35 masks for the new ones. As a result, the wafer cost increases as the technology node decreases, especially when using SOI substrate – much more expensive than other substrates – or copper layers, for which a dedicated clean-room environment is necessary.
The wafer cost also depends on the wafer size. The smallest technology nodes (less than 0.09 μm) entail expensive production equipment only available for 300 mm wafer fab. However, these new technologies allow for fitting more BCD dies on each wafer and, in some cases, for balancing the additional cost resulting from a more complex manufacturing process, specific equipment, and extra raw materials.
Today, very advanced technology nodes (< 0.09 μm) are still exotic. But some major players such as Infineon Technologies, STMicroelectronics, and Intel, which fully develop and manufacture their BCD dies, have already invested in 300 mm fabs to anticipate the future demand in this field and increase their production capacity. Some other companies that have not invested in new foundries have developed a fabless or fablite model, either partially, as in the case of Analog Devices which outsources their BCD die fabrication to TSMC for technology nodes of less than 0.18 μm, or completely, as with Melexis or HiSilicon which partner respectively with X-Fab and SMIC.
About the authors
Sylvain Hallereau is Principal Technology & Cost Analyst at Yole SystemPlus, part of Yole Group (Yole).
Working in close collaboration with the laboratory teams, Sylvain produces reverse engineering & costing reports while also contributing to custom projects, especially focused on solid-state lighting components, sensors, biotechnology devices, and ICs. Together, they define the objectives of the analysis and the most relevant methodology to gain a detailed understanding of the structure of the device. Sylvain then analyzes the results to describe the technology choices made by the leading semiconductor companies and the related process flows and also calculates the cost structure.
Sylvain holds a master’s degree in Microelectronics from the University of Nantes (France).
Belinda Dube serves as a Technology & Cost Analyst at Yole SystemPlus, part of Yole Group.
Belinda’s core expertise is memory technology, especially DRAM and 3D NAND flash memory. At the same time, she also investigates IC technologies as well as advanced packaging.
Belinda’s mission is to develop reverse engineering & costing reports. She also works on custom projects, where she works closely with the laboratory team to set up significant physical & chemical analyses of innovative memory chips
Belinda holds a master’s degree in Instrumentation & Nanotechnology Engineering from INSA (France).