Fan-Out panel-level packaging hurdles

The economics look attractive, but first the industry needs convergence on panel size, process tools, and materials. An article written by Anne Meixner for Semiconductor Engineering, in collaboration with Gabriela Pereira from Yole Group.

Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield.

There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in very high volumes, such as power management ICs for mobile phones, using relatively relaxed RDL dimensions. In addition, the industry has yet to settle on a standard panel size and establish assembly design kits to ensure design-to-manufacturing compliance.

There are several main challenges facing OSATs and their engineering teams:

“We expect to see a significant increase in adoption of FOPLP beyond mobile/wearable applications,” said Monita Pau, strategic marketing director for advanced packaging at Onto Innovation. “There are also a growing number of packaging houses providing FOPLP capabilities.”

The upside for growth in this market is significant. “Looking at the total fan-out packaging market, FOWLP is still the mainstream carrier type, and FOPLP is still considered a niche market, said Gabriela Pereira, semiconductor packaging analyst for Yole Group. “In terms of revenue, Yole Intelligence, in the Fan-out Packaging 2023 report, estimates the FOPLP market was approximately $41 million in 2022[1], and it is expected to show a significant CAGR of 32.5% in the next five years, growing to $221 million in 2028. In fact, FOPLP adoption will grow faster than the overall fan-out market, and its market share, vis-à-vis FOWLP, will move from 2% in 2022 to 8% in 2028. This means that FOPLP is expected to grow in the coming years as more panel lines become available and higher yields provide better cost efficiency.”

That level of cost efficiency is significant. The relative cost savings associated with panels versus round wafers can exceed 20%.

In terms of process capability, FOPLP can be viewed as a technology that straddles fan-out wafer level packaging (FOWLP) and printed circuit board processing. Over the last 10 years, engineering teams at major assembly companies and research institutes have developed panel-level packaging, in some cases by leveraging existing processes and tools…

… Read the full article here.

Source: https://semiengineering.com/