The role of Fan-Out packaging and its future – Interview of STATS ChipPAC – JCET Group

While Fan-Out Packaging has become one of the popular advanced packaging term, its history and adoption started more than a decade ago.

In 2006 where Freescale established its first 200mm pilot line for Redistributed chip packaging (RCP) in Austin (US). In 2008 Infineon created embedded wafer-level BGA (eWLB) and licensed it globally to ASE, Amkor Portugal (formerly Nanium) and JCET Group (formerly STATS ChipPAC). Since then, eWLB has been the most famous FO technology in the Core market (low-end applications). Its long history and proven qualification devices like PMICs, RF transceivers,

Connectivity Module, Audio/Codec module, Radar module and Medical glucose monitor/sensors etc. have provided customers with confidence and is continually being adopted. The ground-breaking moment comes when TSMC invented inFO for Apple A10, application processor for the iPhone 7 commercialized by Apple in 2016. This created a whole new market called High-Density Fan-Out (HD FO). Even after few years of inFO deployments, nobody other than TSMC Qualcomm has been able to achieve HD FO. Not only has inFO attained establishment in APE application, but it is also utilized as a powerhouse technology to penetrate into HPCs and 5G applications.

The new milestone was FOPLP, deemed as a vision previously but now a reality. In 2018, SEMCO and PTI have invested and developed FOPLP for production successfully in 2018. Some view FOPLP as one of the ways to “by-pass” IP of FOWLP which is saturating. Some truly believe FOPLP is the only way to reduce cost. Opinions are highly divided. Pro-FOWLP players are no longer underestimating FOPLP penetration. This is indeed a unique scenario where key players of different business models overlap their Fan-Out offerings with diverse manufacturing strategies. It is exactly because of this that we are seeing split manufacturing paths between FOPLP and FOWLP.

Fan-Out Packaging and its evolutions are built on the solid foundational and have been improving technically into new market and applications over the decade. The future of Fan-Out Packaging is highly dynamic with a series of investments and roadmaps in place by key players which indicates solid advancement. Long-term view remains positive but the current situation can be volatile. Although Fan-Out Packaging market is relatively small, it is expected to grow strongly at a 19% CAGR from 2019 to 2024, reaching a market size of $3.8B, regarding Fan-Out Packaging: Technologies and Market Trends 2019 report by Yole Développement.

FOP business model evolution Yole2019

In this context, Favier Shoo, Technology and Market Analyst from Yole Développement took the opportunity to interview Seung Wook Yoon, Ph.D, MBA, Director/Technology Division at STATS ChipPAC – JCET Group

Favier Shoo (FS): After acquiring STATS ChipPAC in 2015, JCET is currently ranked third among OSATs in terms of 2018 revenue. As an OSAT powerhouse, could you briefly introduce JCET’s business and its activities in fan-out packaging?

Seung Wook Yoon (SWY): Currently, JCET group has two FOWLP technologies: eWLB and FO-ECP. Both solutions are available from STATS ChipPAC and JCAP, respectively. Also, we are in high-volume production for PMIC, RF, connectivity, baseband, audio codec, MCU, MEMS, automotive, controller, etc.

FS: Since 2016, fan-out packaging has been a hot topic because of Apple’s choice to adopt TSMC’s fan-out solution (integrated Fan-Out (inFO) technology) for the A10 APE packaging in the iPhone 7. Do you think fan-out packaging is just a fad, or a genuine packaging option with increasing adoptions?

SWY: FOWLP has advantages over conventional packaging, so it can drive more applications beyond the mobile and consumer markets. For example, automotive, mmWave/5G/AiP, MEMS/sensor, and IoT applications.

FS: In 2018, all key OSAT, IDM, and foundry players had fan-out packaging offers. This remains a steadily-growing market with 19% revenue growth from 2018 ($981M) to 2019 ($1,168). Also, in the long-term, fan-out packaging’s total revenue is expected to grow significantly, at a 25% CAGR from 2018 – 2024. How will fan-out packaging market opportunities affect OSAT strategy and JCET’s position, in particular?

SWY: The FOWLP market is more focused on advanced features, i.e. multi-die, multilayer RDL, and integrated packaging solutions. Also, chiplet package would be a potential market with advanced node devices for network and graphics applications.

FS: Fan-out packaging technology is not only a bridge to chip-package interaction (CPI) mismatch in pitch size, but it is also a viable solution for heterogeneous integration of functionalities in a desired package dimension and design. Moving forward, what do you think are the technical requirements for fan-out packaging, and what are the new applications?

SWY: As demonstrated over the last 10 years, FOWLP technology is ready to support heterogeneous integrationIt proves the capability of multi-layer RLD with finer line width/spacing (ie. 2/2um). As described earlier, automotive, mmWave/5G/AiP, MEMS/sensor, and IoT would be the next markets after mobile/consumer applications.

FS: Fan-out packaging’s key benefit is its ability to integrate dies together flexibly, at thinner thicknesses. It can displace 2.5D interposers with fine L/S fan-out packaging on substrate, as well as flip-chip and advanced substrate. Will fan-out packaging continue to cannibalize and phase-out other packaging technologies?

SWY: FOWLP has its own advantages, as stated in your question… but flip-chip and SiP technology have their own unique merits too. That said, FOWLP and other packaging solutions for heterogeneous integration should go together.

FS: It seems fan-out is also starting to gain adoption in memory packaging. For example, TSMC’s inFO-MS (integrated Fan-Out Memory on Substrate), and PTI’s future plans to include memory devices in FO solutions. Are the players in the supply chain opening a new door to memory fan-out packaging? What is your opinion on this new development?

SWY: It may or may not. Memory packaging has specific requirements due to its business nature, including large volume, in-house capability, and JEDEC standard. For integration it would be a good approach, but monolithic memory packages may have several challenges to overcome.

FS: Other than mobile, multiple drivers like AI, smart automotive (electrification and autonomous driving), 5G, IoT, and hyperscale data centres have emerged which will drive semiconductor industry growth and packaging innovations. Do you think fan-out packaging has a big role to play in this megatrend-driven era?

SWY: FOWLP should have a good position in those applications because it provides unique features such as heterogeneous integration, superior electrical and thermal performance, fine interconnection capability, androbust reliability (ie. AEC Q100 Grade 0/1).

FS: For core FO, the current FOWLP installed-base capacity is enough to sustain existing demand. Core FO YoY market revenue growth for 2017 and 2018 was 21% and 33%, respectively. In 2019, core FO is expecte to show a slower growth of 13% YoY, as compared to prior years. Furthermore, although there was no significant capacity expansion for existing end-products in 2018, fabless continued to push packaging houses for a lower cost. Do you expect demand to be slower in 2019? Will production pick up by 2020 or 2021?

SWY: I understand that new FOWLP solutions are already available on the market, so they would attract more demand if volume and capacity expand in the near-term.

FSH: With TSMC’s InFO being able to package high-end APE for Apple’s iPhone, a new market called high-density fan-out (HDFO) was created. TSMC has been the sole contributor to HDFO since 2016, and the company is not only an advanced foundry for the front end (FE), but also a high-end packaging house for the back end (BE). Which other players do you think can penetrate HDFO and compete against TSMC’s inFO technology and business model?

SWY: It depends on the business model. For HDFO, the assembly yield is the main challenge (with advanced features), so the cost of ownership is the key question due to the expensive die cost. An IDM or foundry has more flexibility to handle these issues.

FS: New players are positioning themselves differently for fan-out packaging. In order to achieve substantial cost-reduction, these entrants are mostly utilizing panel-level packaging for fan-out. Opinions are still divided and strategies are different, but what is your opinion on FOPLP’s appeal to fabless/IDM/foundries? Will FOPLP be utilized for reaching high-end applications?

SWY: New FOWLP solutions with improved assembly yield should appeal to the high-end application market. Also, substrate technology has adopted finer LW/LS capability, so it would merit flip-chip or SiP module to sustain the current business model and baseline capability.
Panel-level FOWLP is mainly for economies of scale, and thus for larger-volume products. For the production of high-end applications, panel-level FOWLP should be ready with competitive manufacturing capability, higher assembly yield, and advanced features.

FS: Some package technologies are considered PLP, but it is FOPLP that is garnering the most attention because of FOWLP’s success and awareness. This attracts players possessing many different business models, including OSATS, integrated device manufacturers (IDMs), foundries, substrate manufacturers, and flat-panel display (FPD) players. Do you think FOPLP will take off? What kind of impact do you expect for all of the players in this supply chain?

SWY: Some panel-level FOWLP players are already in volume production from last year, which proves that panel-level technologies are available and capable. But there should be a very limited number of players, because this technology needs solid business engagement to fill up the line-capacity, along with huge CAPEX and investments.


Dr. Yoon is currently working as director of Technology Division, STATS ChipPAC Singapore, JCET Group.  His major interests are for Advanced Wafer Level Packaging and Wafer Level Integration Technology including eWLB/Fan-out/Fan-in WLP, Bumping, SiP, TSV, IPD and integrated 3D IC packaging.

Prior to joining STATS ChipPAC, He was deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR, Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 300 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging. Currently working as technical committee member of various international packaging technology conferences, EPTC, ESTC, iMAPS, IWLPC and SEMI.


Favier Shoo is a Technology and Market Analyst in the Semiconductor & Software division at Yole Développement, part of Yole Group of Companies. Based in Singapore, Favier is engaged in the development of technology & market reports as well as the production of custom consulting reports.
During 7 years at Applied Materials as a Customer-Application-Technologist in the advanced packaging marketspace, Favier developed a deep understanding of the supply chain and core business values. As an acknowledged expert in this field, Favier has provided training and held numerous technical review sessions with industry players. In addition, he has obtained 2 patents.
Prior to that, Favier worked at REC Solar as a Manufacturing Engineer to maximize production capacity.
Favier holds a Bachelor in Materials Engineering (Hons) and a Minor in Entrepreneurship from Nanyang Technological University (NTU) (Singapore). Favier was also the co-founder of a startup company where he formulated business goals, revenue models and marketing plans.

Related reports:

Fan-Out Packaging: Technologies and Market Trends 2019
Market & Technology report
Samsung and PTI, with panel-level packaging, have entered the Fan-Out battlefield.

Equipment and Materials for Fan-Out Packaging 2019
Market & Technology report
Electronic packaging equipment and materials revenue growth is highly reliant on big players’ investments. A new killer application is needed to fuel robust growth.

Related webcast:

webcast The battlefields of fan-out packaging

The Battlefields of Fan-Out Packaging
All key players with different FO technologies are facing an unavoidable battle of cost and performance trade-off between panel-level vs. wafer-level.