Unlocking GaN’s full potential: an interview with Qromis


Vladimir Odnoblyudov

Co-founder and CTO




Taha Ayari, Ph.D.

Technology & Market Analyst, Semiconductor Substrates & Materials

Vladimir Odnoblyudov

Co-founder and CTO

Vladimir Odnoblyudov, Ph.D., is the co-founder and CTO of Qromis. He has 20 years of experience in optoelectronic and electronic devices, process integration, and wide bandgap semiconductor technologies, holding leadership roles in both startups and Fortune 500 companies. Previously, he was the Director of R&D and Emerging Technologies at Bridgelux, Inc., and the Director of LED Solutions at Micron Technology, Inc., where he led R&D for large diameter GaN wafer and device technology. He also founded and served as CTO of Quanlight, an LED start-up. Vladimir holds a Ph.D. in Electrical Engineering from the University of California San Diego.


Taha Ayari, Ph.D.

Technology & Market Analyst, Semiconductor Substrates & Materials

Taha’s expertise is mainly in power electronics with related WBG materials and emerging semiconductor substrates. He is fully engaged in the development of technology and market products, as well as custom projects. Taha has two years’ experience as a Technology & Cost Analyst at Yole Group, where he focuses on the development of compound semiconductor reverse engineering & costing analyses. Prior to Yole Group, Taha was a research engineer at Georgia Tech Lorraine (Metz, France). He published numerous papers with a particular focus on III-N materials. Taha holds an MSc and a Ph.D. in electrical and computer engineering from the Georgia Institute of Technology (Atlanta, USA).

As an alternative to single-crystal materials, engineered substrates and templates have been proposed, offering lower costs, enhanced performance, and greater functionality. In power electronics, the rise of wide bandgap technologies presents challenges in meeting demand and balancing cost/performance ratios.

According to Yole Group‘s report, Power GaN (2024 edition coming soon), the power GaN market is projected to exceed US$2.5 billion by 2029, boosted by its adoption in high-power and high-end applications such as automotive. Currently, the predominant platform for power GaN is 600V-750V 6-inch GaN-on-Si, which is transitioning to 8-inch wafer sizes and higher voltages.

This shift, coupled with stricter requirements for material quality and cost, presents an opportunity for engineered substrates, as analyzed in the Emerging Semiconductor Substrates report from Yole Group. A notable solution is the QST® wafers (Qromis Substrate Technology) from Qromis.

To gain deeper insights into Qromis’s activities and solutions, Taha Ayari, Technology and Market Analyst at Yole Group, interviews Vladimir Odnoblyudov, Qromis’s CTO and co-founder.

Taha Ayari (TA): Please introduce Qromis and describe the technology underlying your QST substrate. What are the different industries that QST substrates could address?

Vladimir Odnoblyudov (VO): Qromis, founded in 2015 by our President & CEO – Cem Basceri – and me, is a privately held fabless technology innovator headquartered in Silicon Valley (Santa Clara), California. The company focuses on innovative, disruptive, and high-performance WBG semiconductor materials that enable energy-efficient solutions.

More specifically, and as the main focus area, Qromis brings a groundbreaking and commercially engineered substrate solution called QST® (Qromis Substrate Technology) to enable CMOS fab-friendly and scalable GaN power/RF/LED-microLED device wafer solutions and unlock the full potential of GaN for widespread adoption.

As a rapidly growing Silicon Valley-based fabless company, Qromis is driving the commercialization of its patented QST® substrate innovation (protected by close to 300 patents worldwide) by leveraging the manufacturing platforms of its worldwide industrial partners through close collaborations up and down the supply chain.

Qromis, with its licensees and manufacturing partners, Vanguard International Semiconductor Corp. (VIS) and Shin-Etsu Chemical Co., Ltd., is one of the premier players in the rapidly growing, multi-billion-dollar energy-efficient GaN power electronics industry, enabling an unmatched cost, performance, and application scale.

Commercial SEMI-spec and CMOS fab-friendly 200 mm QST® substrates available from Qromis (manufactured by VIS exclusively for Qromis) and Shin-Etsu Chemical (manufactured internally at Shin-Etsu Chemical) enable wafer breakage-free high-volume manufacturing of GaN device wafers, covering all GaN applications including 100 V to 2000 V and beyond high performance discrete and wafer-level monolithic IC power devices, RF devices, and microLED displays. 300 mm QST® substrates are currently being developed for initial shipments in 2024.

Qromis also offers commercial SEMI-spec and CMOS fab-friendly 200 mm GaN-on-QST® epitaxy wafers (manufactured by VIS exclusively for Qromis) for E-mode / D-mode HEMT devices and low dislocation vertical devices.

In parallel, VIS, as a pure-play foundry, offers 200 mm GaN-on-QST® power device foundry services for all industry players. The first generation (Gen1) 650 V E-mode GaN HEMT devices (40 and 150 milliohm) on 200 mm SEMI standard thickness QST® substrates entered production at VIS in the second half of 2022 after passing the full JEDEC reliability tests, including 1000-hr HTRB and HTGB on packaged devices. An example of the initial applications of Gen1 devices is the upcoming commercial fast chargers (65 W and 100 W).

This achievement by VIS, which took only ~3 years from a ground-zero level, marked the establishment of the first 200 mm GaN device foundry services for all industry customers.

The volumes of Gen1 GaN-on-QST® E-mode HEMT devices manufactured are currently ramping for initial 650 V applications, which will be followed by Gen2 devices in the second half of 2024, designed for industrial and automotive applications with additional cost reduction by using three-level metal layer architecture. Gen2 devices, which are currently in the design/pilot shuttle/reliability test stage, will be qualified at a full rating of 650 V hard switching. 1200 V GaN-on-QST® development at VIS is also underway and scheduled to be released by the end of 2025. One of the target applications will be 800 V EV charging.

TA: Could you please explain the added value of Qromis’ QST® Technology? What applications are targeted by Qromis?

VO: In recent years, GaN has become a critical wide bandgap semiconductor material, in demand for next-generation, energy-efficient power electronics. With its higher breakdown strength, faster switching speed, and lower on-resistance, GaN power devices can convert power far more efficiently than Si-based devices and thus enable smaller, faster, lighter, and lower-cost power conversion systems, as well as significantly reduced CO2 footprint. Its figure-of-merit (FOM) and manufacturability in mainstream advanced CMOS fabs are also superior to SiC-based devices.

For these reasons, and also for achieving full sustainability, the demand for GaN has grown considerably in recent years as companies work to develop next-generation, energy-efficient power electronics. While its performance has been commercially demonstrated on conventional substrates (such as Si and Sapphire), widespread GaN adoption requires a scalable and high-yielding manufacturable technology platform enabling economies of scale and a full spectrum of low-cost products, such as lateral and vertical power switches extending from 100 V to 2000 V and beyond, wafer-level monolithic ICs and rectifiers.

Manufacturing GaN power devices on native GaN substrates is still extremely costly, and it is very difficult to scale the GaN substrate diameter to 150 mm, 200 mm, and beyond, including 300 mm.

Manufacturing GaN power devices on non-native substrates like silicon, sapphire, and silicon-on-insulator (SOI) introduces significant challenges due to a large mismatch in coefficient of thermal expansion (CTE), resulting in high stress, wafer breakage, non-SEMI standard thickness, limited wafer diameter and voltage scaling, reliability issues, and increased costs. These limitations restrict the full promise of GaN. 

Scaling up both the substrate size and GaN stack thickness even further and achieving wafer-level monolithic ICs on the current mainstream 150 mm, 650V GaN-on-Si manufacturing platform, even with non-SEMI standard substrate thickness (1 mm or thicker), is extremely challenging due to the significant CTE mismatch between GaN and Si and the IC device crosstalk challenges arising from the conducting Si substrates.

Qromis’ disruptive commercial QST® substrate solution addresses and overcomes these obstacles and unlocks the full potential of GaN. The CMOS fab-friendly and SEMI standard thickness commercial QST® substrates, which are similar to SOI substrates with respect to substrate assembly processing and cost, enable the fabrication of long-awaited commercial high-performance GaN power devices with breakdown voltages ranging from 100 V to 2000 V and beyond, and on advanced 200 mm and 300 mm diameter CMOS manufacturing platforms.

This is achieved by utilizing a polycrystalline, high thermal conductivity and high mechanical strength AlN ceramic core material with a thermal expansion that very closely matches the thermal expansion of the GaN/AlGaN epitaxial layers over a wide temperature. This prevents excessive stress, GaN cracking, or wafer breakage during the cooling stage of the GaN epitaxy growth process.

High thermal conductivity (170-230 W/mK) AlN ceramic core material is encapsulated into a series of thin films on top of which a SiO2 bonding layer is deposited, and a single crystalline Si (111) layer is formed, which serves as the nucleation layer for the epitaxial GaN growth. The Si (111) GaN growth-ready surface can be changed to single crystal GaN, SiC, or other GaN growth-ready surface.

QST® substrates enable not only mainstream lateral GaN power devices but also the long-awaited commercial vertical GaN power switches and rectifiers suitable for high-voltage and high-current applications presently dominated by Si IGBTs and SiC power FETs and diodes.

While the QST® platform enables higher performance and application scale for GaN devices, it also brings a critical economy of scale advantage for device manufacturers and foundries since all GaN devices (power, RF, microLED, and others) can be manufactured on the same CMOS fab-friendly, SEMI-spec platform for efficiency and further cost reduction.

Another important feature that the QST® solution brings is that the QST® substrates are assembled and manufactured in traditional CMOS fabs (similar to mainstream SOI substrates with respect to manufacturing processing and cost) by utilizing energy-efficient mainstream semiconductor process tools with >98% yield and less than 7 days of process cycle time while, e.g., SiC substrates are manufactured in isolated, non-CMOS compatible fabs with crystal growth processes at extreme temperatures >2200oC for several days which result in excessive amounts of power consumption, water cooling, and consumables such as graphite and felt. This is a critical component of the QST® innovation which was carefully designed per the projected cost and sustainability requirements in the industry.

In Yole Group’s Emerging Semiconductor Substrates 2023 report, analysts see that engineered substrates, including QST, will have the highest 2023-2028 CAGR for power electronics, at about 86%.

TA: In your opinion, what are the most promising power applications that GaN-on-QST needs to address to grow significantly?

VO: As VIS has commercially released the initial 650 V devices on its 200 mm CMOS production line, the GaN-on-QST® platform is designed to address not only the mainstream lateral GaN power devices, ranging from 100 V to 2000 V and beyond on advanced 200 mm and 300 mm diameter CMOS manufacturing platforms, but also vertical GaN power switches and rectifiers suitable for high-voltage and high-current applications presently dominated by Si IGBTs and SiC power FETs and diodes. The growth landscape for the GaN-on-QST® platform includes both discretes and wafer-level monolithic ICs.

Automotive and industrial-quality 650 V GaN-on-QST® power devices on 200 mm platforms are expected to set the stage for initial significant growth, followed by 900 V and 1200 V for higher voltage applications, such as EV inverters. Additionally, 650 V and beyond wafer-level monolithic ICs will be part of the significant growth and adoption of GaN-on-QST®.

TA: When do you expect significant adoption of the QST substrate? Could you comment on the supply strategy of this substrate to satisfy an increase in demand?

VO: Overall, the GaN market is expected to grow further over the next two years, with a significant CAGR thereafter. The demand from sophisticated customers for scalability and sustainability, as well as confident roadmaps from IDMs and foundry GaN device manufacturers (for their application ramp decisions) will accelerate QST® substrate adoption with its unmatched performance, applications, and economies of scale.

Both VIS and Shin-Etsu Chemical, as Qromis’s manufacturing partners and licensees, are steadily ramping up their production capabilities for the demand projections from Qromis and also their existing customers’ projections. Overall, their projections include manufacturing tens of thousands of QST® substrates monthly. If needed, our current second sourcing model between Qromis and Shin-Etsu Chemical can be extended further by enabling additional QST® substrate manufacturer(s).

GaN epiwafer is the key building block for power GaN devices, accounting for around 30%-40% of the component’s production cost, according to Yole Group’s analysis.

TA: Do you think GaN-on-QST can provide a cost advantage over GaN-on-Si or GaN-on-Sapphire? What about the pricing of the QST substrate?

VO: QST® substrates are similar to mainstream SOI substrates with respect to substrate assembly processing and cost. As such, the pricing is very similar to SOI in volume shipments, i.e., significantly cheaper than SiC. At such volume pricing levels, QST® brings a highly competitive and sustainable device cost and business economic advantage compared to alternative platforms such as GaN-on-Si and GaN-on-Sapphire, as shown by the following key features (non-exhaustive):

  • Scalability from 200 mm to 300 mm and beyond,
  • SEMI-spec thickness and compatible with mainstream CMOS fabs (i.e., no dedicated manufacturing line requirement),
  • Enabling foundry economics,
  • No epitaxy cracking or wafer breakage (very high mechanical strength); low stress,
  • <5 mm edge exclusion,
  • High epitaxy yield and reduced epitaxy cost,
  • High device and backend yield (>90%),
  • High reliability and ruggedness due to extensive epitaxy budget,
  • Cooler devices due to high thermal conductivity AlN ceramic core,
  • More

Here are some additional details regarding GaN epiwafer being the key building block for power GaN devices, accounting for around 30%-40% of the component’s production cost, according to Yole Group’s analysis, Power GaN 2023.

With the CTE-matched structure, GaN epitaxy layers on QST® do not require complex and costly strain management layers, which are essential for GaN-on-Si and other heteroepitaxy platforms. As such, the GaN-on-QST® platform enables very significant GaN epitaxy cost reduction, process simplification, and increased reactor uptime via reduced process times while yielding thicker GaN layers.

A drastic cost and performance improvement from a comparative, side-by-side study led by Shin-Etsu Chemical, which was presented at 2023 SEMICON Taiwan, shows that GaN epitaxy growth time is cut in HALF for GaN-on-QST® compared to GaN-on-Si. This opportunity for a simplified and low-cost GaN epitaxy process will further propel GaN-on-QST® adoption.

The use of the CTE-matching technology results in crack-free edges of GaN-on-QST® epitaxy wafers for a wide variety of thicknesses and applications, which significantly improves device yield by enabling a small edge exclusion of ~5 mm and eliminating potential particle and flake generation areas.

TA: Yole Group expects a transition to an 8-inch wafer size for power GaN in the coming 3-5 years. Can QST substrate be an accelerator of this transition? What about 12-inch?

VO: As discussed above, 200 mm GaN-on-QST® is already in commercial production at VIS (since the second half of 2022), which serves as an example of how QST® can accelerate the transition to 200 mm across the industry, IDMs, and foundries. With that, VIS still remains the first and only foundry with a fully qualified and officially released 200 mm 650V GaN device platform.  

Both Qromis and Shin-Etsu Chemical are actively working with device manufacturers to help them with a smooth transition to 200 mm or to establish new entrants’ 200 mm fabs.

300 mm QST® substrates are currently being developed for initial shipments in late 2024. Qromis expects that 300 mm GaN scalability will also be one of the very critical elements for further GaN competitiveness, adoption, and further investments by device manufacturers and their customers.

800 V powertrain systems for EVs are growing in the automotive industry, requiring 1200 V devices, which are being supplied by SiC players.

TA: Do you see QST substrates as an enabler for 1200V power GaN devices compared to Si or Sapphire? Could GaN-on-QST compete with SiC for this application in terms of performance and cost?

VO: As we discuss in detail, 1200 V is one of the critical segments that the GaN-on-QST® platform will enter, with superior performance, cost, and scalability compared to Si, sapphire, and SiC.

In addition to the recent publication by imec on the establishment of a 1200 V, 200 mm GaN-on-QST® device baseline with very good device parameters and a high breakdown of ~1800 V, VIS has also announced publicly its development and product release schedule on the 200 mm platform through the Taiwan government’s additional funding for this important project. VIS has already achieved >2400 V hard breakdown voltage.

With that, the simple answer is GaN-on-QST® will expand to 1200 V and beyond with its highly competitive and scalable features.

TA: Recent announcements from ShinEtsu and Oki indicate that QST can enable vertical GaN devices. Can you elaborate more on the progress? When can we expect this technology to be commercialized?

VO: As background, vertical device architectures have several advantages over lateral devices. First, the fields are vertical over the bulk of the device rather than peaking at the surface, improving the device’s reliability and stability (dispersion). Second, there is a potential for avalanche robustness, which has not been demonstrated for lateral devices. And lastly, the area of lateral devices becomes prohibitively large when scaling to large voltages due to the increased gate-drain distance, whereas for vertical devices, the thickness of the epilayer (drift region) determines the breakdown voltage.

Most of the vertical GaN devices to date are grown on bulk GaN substrates which are small in substrate size and expensive. Si wafers are available in large substrate sizes, but the total GaN stack thickness that can be grown is very limited due to the CTE mismatch barrier.

The CTE-matched QST® substrates offer a breakthrough in the growth of thick GaN layers. As we demonstrated in an earlier work, GaN Schottky barrier diodes on QST® exhibited a forward I-V characteristics comparable to those on GaN-on-GaN native substrates.

Recently, results from a demonstration study led by OKI Electric Industry (OKI) revealed that GaN epitaxy or GaN device layers on QST® substrates can be successfully separated and bonded to different substrates for realizing vertical GaN devices and high-performance lateral GaN devices (e.g. HEMTs on high thermal conductivity substrates). This significant achievement utilized OKI’s proprietary lift-off technology called Crystal Film Bonding (CFB®), which has been used by the company for microLEDs on IC chips for LED printers since 2012 (over 100 billion microLEDs processed by CFB®).

The CTE-matching feature of GaN-on-QST® enables this successful achievement since very low stress is critical for successfully separating GaN layers. Also, having different layers under the Si (111) surface of QST® (engineered layers) enables a variety of selective lift-off process options.

Overall, this is a process module option available from OKI for manufacturing vertical GaN devices on QST®.

Currently, in collaboration with Shin-Etsu Chemical, OKI is working closely on a commercialization path for the industry. This could include licensing or service through OKI.

TA: Would you like to share any closing thoughts or additional insights for our readers?

VO: First of all, thank you very much for this very timely and insightful interview.

Overall, Qromis and its partners’ mission is to propel GaN adoption and enable device manufacturers to deliver robust, cost-effective, and scalable GaN device solutions to their customers.

I truly believe that different materials, including Si, GaN, SiC, and other emerging ones such as Ga2O3, AlN, and diamond, and on different substrate manufacturing platforms will co-exist to address energy efficient solutions with a wide variety of applications in power, RF, microLEDs and more; the choice will depend on specific applications, performances, scalability, sustainability, and business economics.

For GaN specifically, further investments into resources and systematic studies across different manufacturing platform options by IDMs and foundries are needed to prepare the next stage of adoption, ramps, and high-quality delivery requirements with reasonable and sustainable lead times and roadmaps. From the Qromis side, we are fully committed to working with all IDMs, foundries, material companies, and research institutions to enable the adoption of GaN.

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