The idea of a multi-chip product has been around for some time, for the purposes of achieving a higher functioning system made up of smaller components. We have the mainframe CPU IBM 3081, introduced in 1980, for instance. This was made up of multiple chips, packaged separately, and integrated onto a larger substrate.
However, the vast majority of processors we encounter have been of the monolithic variety, where all the functions of the processor exist on one piece of silicon.
As the features of the processors have continued to expand, the complexity of their manufacture has grown as well. The rate at which the design complexity has grown, and the corresponding growth in the capabilities of the manufacturing to accommodate, is known as Moore’s Law. A discussion about the recent excitement on chiplets is difficult without some mention of this decades-old observation.
Well, in the same paper that stands as the basis for the Law that bears his name, Gordon Moore had this to say about the evolution of a technology that encompasses what we now know as chiplets: “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected” (1).
For an observation made 58 years ago, what is it about the current moment that has brought so much attention to this design philosophy?
Yole Intelligence proposes today an overview of the chiplet’s technologies and behind that the business opportunities. John Lorenz, Senior Technology & Market Analyst invites us to deep dive into the technology and get a better understanding of the links between chiplets and advanced packaging. In addition, he underlines the multiple benefits for each application.
This analysis is based on Yole Intelligence’s products: Processor Market Monitor – High-End Performance Packaging (2023 edition coming soon) – Advanced Packaging Monitor… Yole Intelligence is a Yole Group company.
From the perspective of each solution, certainly you have the fact that the designing company chose to pursue a chiplet design as the main reason for its existence. However, we see that a number of factors have reached the right conditions, primed for an approach different than the same-old monolithic. These come down mainly to die size, front-end wafer processing cost, engineering costs for new designs on new nodes, and the maturity and sophistication of packaging solutions. Here at Yole Intelligence, we have developed a cost model for chiplet-based solutions, simulating the effect that these factors have on the economics of making the design decision between monolithic or chiplet. This is a concept particularly explored in Yole Intelligence’s research, such as the quarterly Processor Market Monitor.
Monolithic die size
The innovation engine behind Moore’s Law is what has made it possible that an ever-increasing level of device integration can continue to fit into the same physical size. For example, if the lithography shrink enables 30% smaller building blocks, then one can add 42% more circuitry without increasing the die size. This has been roughly the pace of logic shrink for decades. However, while logic tends to scale well, not all semiconductor devices enjoy that advantage, for example I/O which can contain analog circuitry, scales at about half the rate of logic, and for the most recent transition to 3nm by TSMC, SRAM cell size scales almost not at all. Since a full SOC requires not just logic gates but many different types of device circuitry, and a minimum level innovation to maintain market competitiveness, designers have started to choose to design larger monolithic dies. The hazard of larger dies is in the impact to yield, since as a die becomes larger, it carries a higher probability that it will contain enough critical defects that render it dysfunctional.
Wafer processing cost
Lithography shrink does not come cheaply, as changing transistor shape and size only comes with a combination of higher-priced equipment and longer processing times. Therefore, it follows that a wafer processed on 7nm cost more than one processed at 14nm, and 5nm costs more than 7nm, and so on… As we examine this trend in our cost model, we see a clear trend that as the wafer price increases, the economics for chiplet approaches become more attractive than monolithic.
Engineering cost for new designs on leading-edge nodes
Each new chip design requires design and engineering resources, and because of increasing complexities of new nodes, the typical cost of a new design has grown for each newer process node. This creates further incentive to create designs that can be reused. The chiplet design philosophy makes this possible, as new product configuration can be achieved by just changing the number and combination of chiplets, rather than spinning up a new monolithic design. For example, 4 different processor varieties can be created from a single tape-out, by integrating a single chiplet into 1-, 2-, 3-, and 4-die configurations. This would have required 4 individual tape-outs if done exclusively through a monolithic approach.
Cost and sophistication of advanced packaging solutions
Very much an enabler of this growing chiplet trend is the maturity of how chiplets can connect to each other. Depending on the function of the final product, the die-to-die interconnect needs to allow for high data transfer speeds and low power consumption. Technologies such as hybrid bonding, silicon bridges, interposers and advanced substrates are making more die-to-die communication possible. These are the kinds of technologies discussed in detail in Yole Intelligence’s report High-End Performance Packaging. As these technologies gain in maturity, they become cheaper to implement, and further enable to the growing chiplet trend. Of course, the package for a monolithic solution should be generally cheaper than that of an equivalent chiplet solution. But when balanced against the chiplets’ yield benefits, we see a trend emerge that would dictate better economics for chiplets at smaller die sizes as the chiplet packaging cost premium decreases.
Chiplets, a design philosophy that has been around for decades, is finding its moment now. The motivating factors have reached critical levels, such as monolithic die size demands and wafer processing costs. The enabling factors are beginning to reach maturity, such as high-performance packaging solutions. Up until now, the main players to take advantage of chiplets are among the largest semiconductor companies in the world, and have done so with in-house approaches, using proprietary interconnect IP, and assembled. However, as interconnect standards such as UCIe and OCP’s Bunch-of-Wires gain attention, there will be fewer barriers of entry for smaller firms to contribute to the nascent chiplet ecosystem.
About the author
John Lorenz is a Senior Technology and Market Analyst, Computing & Software within the Semiconductor, Memory & Computing division at Yole Intelligence, part of Yole Group. John is engaged in the development of market and technology monitors for the logic segment of advanced semiconductors, with a primary focus on processors. Prior to joining Yole Intelligence, John held various engineering and strategic planning roles over 15 years at Micron Technology. John has a Bachelor of Science degree in Mechanical Engineering from the University of Illinois Urbana-Champaign (USA), with a focus on MEMS devices.
This article has been developed in collaboration with Emilie Jolivet, Director, Semiconductor Memory & Computing at Yole Intelligence, part of Yole Group.
(1) Cramming More Components onto Integrated Circuits, April 19, 1965 edition of Electronics.