Next-generation chips: is semiconductor testing ready?

Innovation in semiconductor testing is not keeping pace with chipmakers’ requirements for the next generation of chips, constraining development and driving up the cost of testing.

Chipmakers are still trying to determine the best testing solutions for the next generation of semiconductors as they find it harder to eliminate bad wafers and die as early as possible from the production process. Even when die has been packaged, there is a complex trade-off between how much to spend on the final test of the package versus the cost to the user or supplier if the device fails while in use.

The cause of the problem is two-fold: chips are getting more complex, and the suppliers of test consumables are falling behind in meeting the market’s needs. Test consumables are the critical parts (probe cards, test and burn-in sockets, and interface boards) that connect the test system to the wafer, die, or package. Chipmakers want to make more advanced devices but are coming up against the limits of test capabilities.

The semiconductor industry spent $13.4 billion on test equipment and consumables in 2023, accounting for 2.5% of industry revenues and growing. Yole Group projects that the test equipment market will expand at a compound annual growth rate (CAGR) of 6.2% between 2023 and 2028, with test consumables growing at 6% year after year.

This snapshot is an extract of both Yole Group’s quarterly Market Monitors: Semiconductor Test Equipment Market Monitor and Semiconductor Test Consumables Market Monitor.

Testing costs were previously in decline as companies successfully increased every year the number of chips they could test simultaneously in a single test cell. However, for many applications, the industry has reached the upper limit of parallel testing and, since passing the 14nm process node, has been unable to find ways to offset the higher costs associated with testing ever more complex devices.  

Chips now undergo as many as six stages of testing, from wafer acceptance, wafer sort, wafer level burn-in, package test, burn-in test, and testing at the system level – which is critical for applications such as the newest generations of smartphones, automotive and Artificial Intelligence (AI). Testing chips is expensive and getting more so, but the cost of chips failing when used in an electronics system can be several orders of magnitude higher. This means chipmakers have the tricky challenge of balancing spending on tests and the risk of a device failing in the field. Finding the right balance is not easy, and this explains why there is so much variety in test solutions between chipmakers.

John West remarks, “Advanced packaging technology and the growing number of dice in a package are big factors driving up the cost of testing. It has become critical to perform a thorough test of each die on the wafer to reduce the possibility of a bad die getting into a package that contains multiple good die. The solution requires probe cards with high probe pin counts and pin densities, longer test times, and more sophisticated thermal management of the test environment. This means more expensive equipment and consumables, and more of them as test times expand.”

The likes of Apple and Qualcomm are pushing existing technologies as hard as they can, but they are compelled to make many compromises with their chip designs to accommodate what their test engineers and suppliers can deliver. They typically design test solutions alongside their chip designs to ensure that they remain within these constraints.

“We are in a situation where the industry has a clear technology roadmap to get below the sub 1nm technology node at the front end and a range of packaging solutions to optimize the performance of these chips. The industry doesn’t yet have a clear understanding of what the test solution for these devices will look like. Test technology isn’t responding quickly enough. It isn’t only a supplier problem – it’s a physics problem,” commented John West.

Automotive is another area where costs are growing. In the recent past, most of the chips going into automotive applications were based on mature semiconductor technologies for which the testing solutions are well understood. However, the introduction of Advanced Driver Assistance Systems (ADAS), which use chips at the 7nm node, and electric vehicles requiring power devices made on SiC substrates is new territory for the automotive test community.

Consolidation in the semiconductor testing market has accelerated with an increase in merger and acquisition activity since 2018. Suppliers in the test ecosystem can see the need for advanced solutions is a bottleneck and are responding by acquiring customers or suppliers to leverage more value from the supply chain. Vertical integration to gain access to the best technologies required for next-generation chip testing is a clear market differentiator that can give firms a competitive advantage.

The number of acquisitions is growing rapidly, especially in the printed circuit board (PCB) segment, where many companies have been acquired or units from large conglomerates have been spun out.

It remains to be seen whether the use of AI in data analytics may be able to help optimize testing to overcome some of the current constraints.

While manufacturing and packaging solutions for semiconductors for the next 5-7 years are known, there is no clear testing solution – either from a technological or economic perspective.

Current test solutions are fluid as chipmakers try to figure out the least bad choice, driving innovation in the test space to close the gap. All this means that the semiconductor testing market is dynamic, in terms of both technology and market evolution.

Follow Yole Group’s analyses to stay on top of the latest semiconductor developments. Stay tuned!

John West is Business Line Deputy Director of the Manufacturing & Global Supply Chain activities at Yole Group.

He has over 20 years of industry experience and a successful track record in various strategy and consulting projects.

John has a Bachelor’s degree in Medical Physics from King’s College London and an MBA from Cranfield School of Management.